ARM Cortex-M

The ARM Cortex-M is a group of 32-bit RISC ARM processor cores licensed by ARM Holdings. The cores are intended for microcontroller applications, and consists of the Cortex-M0, Cortex-M1, Cortex-M3, Cortex-M4.^[1][2][3][4]

Contents 1 Overview 1.1 ARM license 1.2 Silicon customization 1.3 Instruction set 2 Cortex-M0 2.1 Features 2.2 Implementations 3 Cortex-M1 3.1 Features 3.2 Implementations 4 Cortex-M3 4.1 Features 4.2 Implementations 5 Cortex-M4 5.1 Features 5.2 Implementations 6 Development tools 7 Documentation 8 See also 9 References 10 Further reading 11 External links

Overview

ARM license

ARM Holdings does not manufacture and sell CPU devices based on its own designs, but rather, licenses the processor architecture to interested parties. ARM offers a variety of licensing terms, varying in cost and deliverables. To all licensees, ARM provides an integratable hardware description of the ARM core, as well as complete software development toolset, and the right to sell manufactured silicon containing the ARM CPU.

Silicon customization

Integrated device manufacturers (IDM) receives the ARM Processor IP as synthesizable RTL (written in Verilog). In this form, they have the ability to perform architectural level optimizations and extensions. This allows the manufacturer to achieve custom design goals, such as higher clock speed, very low power consumption, instruction set extensions, optimizations for size, debug support, etc.

ARM Cortex-M Optional Features^{[5][6][1][2][3][4]}

ARM Cortex-M	SysTick Timer	Bit Banding	Memory Protection Unit (MPU)
Cortex-M0	Optional	No	No
Cortex-M1	Optional	No	No
Cortex-M3	Yes	Optional	Optional
Cortex-M4	Yes	Optional	Optional

Note: Most Cortex-M3 and M4 chips have Bit-Banding and MPU, but software should validate existance before attempting to use.^[7]

Instruction set

The Cortex-M0 and M1 are based upon the ARMv6-M architecture,^[5] the Cortex-M3 is based upon the ARMv7-M architecture,^[6] and the Cortex-M4 is based upon the ARMv7-ME architecture.^[6] The architectures are binary instruction upward compatible from ARMv6-M to ARMv7-M to ARMv7-ME. Binary instructions available for the Cortex-M0 and M1 can execute without modification on the Cortex-M3 and Cortex-M4. Binary instructions available for the Cortex-M3 can execute without modification on the Cortex-M4.^[5][6]

All four Cortex-M cores implement a common instruction subset that consists of: Thumb subset, Thumb-2 subset, multiply. The Cortex-M0 and M1 include all older Thumb instructions, except new instructions (CBZ, CBNZ, IT) which were added in ARMv7-M architecture. The Cortex-M0 and M1 include a minor subset of Thumb-2 instructions (BL, DMB, DSB, ISB, MRS, MSR).^[5][6]

The Cortex-M0 and M1 were designed to be the smallest size possible, thus have the least instructions of the Cortex-M family. The Cortex-M3 adds a 3 Thumb instructions and all Thumb-2 instructions plus a 10-12 cycle hardware divide and saturated math instructions. The Cortex-M4 then adds DSP instructions and optional single-precision floating point unit.^[5][6] If the Cortex-M4 has the floating point unit it is known as the Cortex-M4F.

ARM Cortex-M Instruction Sets^{[5][6][1][2][3][4]}

ARM Cortex-M	Thumb	Thumb-2	Hardware Multiply	Hardware Divide	Saturated Math	DSP Extensions	Floating Point	ARM Architecture
Cortex-M0	Most	Subset	1 or 32 cycle	No	No	No	No	ARMv6-M [5]
Cortex-M1	Most	Subset	3 or 33 cycle	No	No	No	No	ARMv6-M [5]
Cortex-M3	Entire	Entire	1 cycle	Yes	Yes	No	No	ARMv7-M [6]
Cortex-M4	Entire	Entire	1 cycle	Yes	Yes	Yes	Optional	ARMv7-ME [6]

Note: The Cortex-M0 and M1 doesn't include these Thumb instructions: CBZ, CBNZ, IT.^[5][6]
Note: The Cortex-M0 and M1 only include these Thumb-2 instructions: BL, DMB, DSB, ISB, MRS, MSR.^[5][6]

Cortex-M0

Features

Key features of the Cortex-M0 core are:^[1]

• ARMv6-M architecture^[5]
• Instruction Sets
  • Thumb (most), missing CBZ, CBNZ, IT.
  • Thumb-2 (subset), only BL, DMB, DSB, ISB, MRS, MSR.
  • 32-bit hardware multiply, 1-cycle or 32-cycles (silicon option)
• 3-stage pipeline

Implementations

The following IC chips vendors have developed microcontrollers based on the Cortex-M0 core:

• Energy Micro EFM32 Zero Gecko family
• NXP LPC11xx, LPC12xx families
• nuvoTon NuMicro family
• STMicroelectronics STM32 F0 family

Cortex-M1

Features

Key features of the Cortex-M1 core are:^[2]

• ARMv6-M architecture^[5]
• Instruction Sets
  • Thumb (most), missing CBZ, CBNZ, IT.
  • Thumb-2 (subset), only BL, DMB, DSB, ISB, MRS, MSR.
  • 32-bit hardware multiply, 3-cycle or 33-cycles (silicon option)

Implementations

The following FPGAs vendors support the Cortex-M1 as soft-cores:

• Actel FPGAs
• Altera FPGAs
• Xilinx FPGAs

Cortex-M3

Features

Key features of the Cortex-M3 core are:^[8][3]

• ARMv7-M architecture^[6]
• Instruction Sets
  • Thumb (entire)
  • Thumb-2 (entire)
  • 1-cycle 32-bit hardware multiply, 2-12 cycle 32-bit hardware divide, saturated math support
• 3-stage pipeline with branch speculation
• 1 to 240 physical interrupts, plus NMI
• 12 cycle interrupt latency
• Integrated sleep modes
• 8 region memory protection unit (MPU) (silicon option)
• 1.25 DMIPS/MHz
• 90 nm implementation^[9]
  • 32 µW/MHz
  • 0.12 mm²

Implementations

The following IC chips vendors have developed microcontrollers based on the Cortex-M3 core:

• Actel SmartFusion family
• Atmel SAM3 family
• Cypress Semiconductor PSoC 5
• Energy Micro EFM32 Tiny Gecko, Gecko, Leopard Gecko and Giant Gecko families
• Fujitsu FM3 family
• NXP LPC13xx, LPC17xx, LPC18xx families
• STMicroelectronics STM32 F2, F1, L1, W families
• Texas Instruments Stellaris, TMS470, some OMAP 4 families
• Toshiba TX03 Series

Cortex-M4

Features

Conceptually the Cortex-M4 is a Cortex-M3 plus DSP Instructions, and optional Floating Point Unit. If the core contains the floating-point unit, it is known as the Cortex-M4F, otherwise it is Cortex-M4. Key features of the Cortex-M4 core are:^[4]

• ARMv7-ME architecture^[6]
• Instruction Sets
  • Thumb (entire)
  • Thumb-2 (entire)
  • 1-cycle 32-bit hardware multiply, 2-12 cycle 32-bit hardware divide, saturated math support
  • DSP extension: Single cycle 16/32-bit MAC, Single cycle dual 16-bit MAC, 8/16-bit SIMD arithmetic.
  • Floating-Point extension (silicon option): Single-precision floating point unit, IEEE-754 compliant. This Floating-point extension is called the FPv4-SP extension.
• 3-stage pipeline with branch speculation
• 1 to 240 physical interrupts, plus NMI
• 12 cycle interrupt latency
• Integrated sleep modes
• 8 region memory protection unit (MPU) (silicon option)
• 1.25 DMIPS/MHz

Implementations

The following IC chips vendors have developed microcontrollers based on the Cortex-M4 core:

• Atmel SAM4 family (Cortex-M4)
• Freescale Kinetis families (Cortex-M4 and Cortex-M4F)
• STMicroelectronics STM32 F4 family (Cortex-M4F)
• Texas Instruments Stellaris LM4F family (Cortex-M4F)

Development tools

Development toolchains

• TASKING VX-Toolset by Altium.
• TrueSTUDIO by Atollic.
• Embedded Workbench for ARM by IAR.
• MDK-ARM by Keil.
• CrossWorks for ARM by Rowley Associates.
• LPCXpresso and Red Suite 4 by Code Red Tech.
• Sourcery CodeBench by Mentor Graphics.
• GNU GCC toolchain via YAGARTO. Building GCC From Scratch

Free C software libraries

• libfixmath - Q16.16 fixed point math library.

Real-Time Operating Systems (RTOS)

• BeRTOS
• ChibiOS/RT
• FreeRTOS, OpenRTOS, SafeRTOS^[10]
• FunkOS
• Milos^[11]
• RT-Thread
• ScmRTOS^[12]
• SDPOS^[13]
• ThreadX
• µC/OS-II, µC/OS-III
• µTasker
• Unison RTOS

Debugging tools (JTAG / SWD)

• J-Link and J-Trace by Segger, includes utility to reset STM32 option bytes.^[14]
• OpenOCD, open source GDB server supports a variety of JTAG probes.

Non-C/C++ Computer Languages

• Lua - eLua.
• Python - Python-on-a-chip.

Documentation

The amount of documentation for all ARM chips is daunting, especially for newcomers. The documentation for microcontrollers from past decades would easily be inclusive in a single document, but as chips have evolved so has the documentation grown. The total documentation is especially hard to grasp for all ARM chips since it consists of documents from the IC manufacturer and documents from CPU core vendor (ARM Holdings).

A typical top-down documentation tree is: high-level marketing slides, datasheet for the exact physical chip, a detailed reference manual that describes common peripherals and other aspects of physical chips within the same series, reference manual for the exact ARM core processor within the chip, reference manual for the ARM architecture of the core which includes detailed description of all instruction sets.

Documentation Tree (top to bottom)

1. IC Manufacturer Marketing Slides.
2. IC Manufacturer Datasheets.
3. IC Manufacturer Reference Manuals.
4. ARM Core Reference Manuals.^[1][2][3][4]
5. ARM Architecture Reference Manuals.^[5][6]

IC Manufacturers usually have additional documents, including: evaluation board user manuals, application notes, getting started with development software, software library documents, errata, and more.

See also

• ARM architecture, List of ARM microprocessor cores
• Microcontroller, List of common microcontrollers
• Embedded system, Single-board microcontroller
• JTAG, SWD

References

Further reading

• The Definitive Guide to the ARM Cortex-M0; 2nd Edition; Joseph Yiu; Newnes; 552 pages; 2011; ISBN 978-0123854773. (Online Sample)
• The Definitive Guide to the ARM Cortex-M3; 2nd Edition; Joseph Yiu; Newnes; 479 pages; 2009; ISBN 978-1856179638. (Online Sample)

External links

Official

• ARM Cortex-M Website, arm.com
• Quick Reference Cards for Instruction Sets: Thumb, ARM and Thumb-2, Vector Floating Point

Cortex-M Series	ARM Website	ARM Core	ARM Architecture
M0	M0	M0 r0p0	ARMv6-M
M1	M1	M1 r1p0	ARMv6-M
M3	M3	M3 r2p0 M3 r1p1 Errata	ARMv7-M
M4	M4	M4F r0p1 Errata	ARMv7-ME

Other

• Migrating from ARM7TDMI to Cortex-M3, arm.com
• RISC vs. CISC in the mobile era